Advanced integrated circuits with MOS transistors commonly have gate and channel structures formed of multiple elements with complicated three-dimensional shapes. For example, transistors with silicon-germanium (Si—Ge) epitaxial elements typically etch silicon in the transistor substrate adjacent to the transistor gates to form trenches for subsequent growth of Si—Ge epitaxial material. Measurement and control of complex three-dimensional structures, such as MOS transistor structures in which source and drain regions have been etched after gate formation in preparation for selective epitaxial growth of germanium containing silicon, in a manufacturing environment is critical to maintaining electrical parameters such as transistor on-state drive currents and off-state leakage currents within specified limits for integrated circuits in high volume production. Commonly used metrology methods for measuring structures in integrated circuits have serious disadvantages for complex three-dimensional structures, for example, structures with undercut features. Top-down Scanning Electron Microscopy (SEM) lacks the resolution to provide detailed profile information. Transmission Electron Microscopy (TEM) is costly, slow and has limited sample size. Atomic Force Microscopy (AFM) profilometry is slow and has limited sample size. Other profilometry techniques are also slow, have limited sample sizes, and typically have insufficient resolution. Scatterometry has difficulty modeling structures with multiple elements such as the multiple gate spacer elements in advanced MOS transistors.